Welcome from Deepak Kumar Tala
It’s apple picking season in many parts of the world, and the tantalizing variety of fresh apples is enormous. Evidently, there’s an apple variety for every letter in the English alphabet.
The wide variety reminds me of SmartDV’s large portfolio of Design and Verification IP. While there are approximately 26 varieties of apples, SmartDV boasts more than 800 products covering most design and verification needs. And that number continues to grow.
In this issue of Get Smart, we focus on the newest editions to our portfolio — Memory Models, Verification IP and Design IP available for most memory types and derivatives. Memories are ubiquitous in system design and the ability to efficiently model, design and verify them is critical. That’s why we’ve invested heavily in supporting all three of these memory-targeted solutions and one reason why our relationships with the largest memory vendors are our priority. As with all of our relationships, they are built on our expertise and customer support, helping us maintain our ability to offer a large selection of Memory Models, Design IP and Verification IP.
I hope you enjoy yourself if you go apple picking this season. You might think of SmartDV and its broad selection of Design and Verification IP. We are committed to being your “go-to” vendor for all of your Design and Verification IP needs.
Please enjoy the newsletter and send us your feedback. Comments, suggestions and questions are welcome.
Deepak Kumar Tala
Managing Director
Our Technical Distinction: Spotlight on Memory Design and Verification
It is hard to conceive of an SoC, ASIC, microcontroller or system that does not include semiconductor memories of various types. Memories are ubiquitous in electronic system design, and SmartDV has developed a robust portfolio of Memory Design and Verification IP and Memory Models to support both the design and verification of systems that contain memories.
SmartDV’s portfolio includes memory controller Design IP for all derivatives of DDR, LPDDR and Flash and supports the DDR PHY Interface (DFI) specification. Memory verification IP is available for DDR, GDDR, ONFI, TCAM, FLASH, HBM, non-volatile memories, DIMM and others.
SmartDV also offers a wide variety of Memory Models. Its Memory Models come complete with a Memory Verification IP suite that incorporates the Controller Verification IP agent and Memory Model with its slave interface. The SmartDV Controller Verification IP agent helps verify an actual memory DUT, and the SmartDV Memory Model aids in verifying a Memory Controller DUT. SmartDV Memory Models support almost all methodology and language environments, including SystemVerilog, VMM, OVM, UVM, SystemC, Verilog and Specman.
A key competitive advantage offered by SmartDV is its team of over 250 design engineers and its in-house proprietary compiler technology. The compiler supports the rapid development of new Design IP, Verification IP, Memory Models and other IP. It is also used to modify or customize IP to address customer-specific requirements. This combination of dedicated technical resources and compiler technology has enabled SmartDV to grow its IP portfolio to more than 800 unique products — by far the largest portfolio in the industry.
We invite you to browse SmartDV’s product directory for IP solutions for your most critical design or verification needs.
SmartDV in the News
SmartDV Provides Broad Portfolio of Memory Modeling, Design and Verification Solutions
From EEWeb: Design and Verification IP: Insights from a SmartDV Insider
See SmartDV at ...
CSIA-ICCAD Conference
November 11-12
Wuxi Taihu International Expo Center
Wuxi, China
Design Automation Conference
December 5-9
Moscone Center West
San Francisco
SemIsrael Expo
New Date: December 13
Avenue Convention Center
Airport City, Israel
Connect with SmartDV at:
Email: demo@smart-dv.com
Website: www.Smart-DV.com
Linkedin: https://www.linkedin.com/company/smartdv-technologies/about/
Twitter: @SmartDV