AMBA ATB Assertion IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC. The SmartDV's AMBA ATB Assertion IP is fully compliant with standard AMBA ATB 1.0/1.1 Specification.
AMBA ATB Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA ATB Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant to ARM AMBA 3 ATB (ATB v1.0) and AMBA 4 ATB (ATB v1.1) Protocol.
- Supports all ARM AMBA ATB data, byte and ID widths.
- Supports Flow control and Flushing
- Supports for ATB1.1 Synchronization Request and triggering operations.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV ATB VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure ATB Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA ATB Assertion Env
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SmartDV's AMBA ATB Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
