DMA Controller with OCP interface is full featured, easy-to-use, synthesizable design that can be used with OCP based systems as a controller to transfer data directly from system memory to IP core or from IP core to system memory. Through its compatibility, it provides a simple interface to any IP core with the appropriate logic in between.
DMA Controller with OCP IIP is supported natively in Verilog and VHDL
- Features
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- Supports 1-16 channel DMA Transmit and DMA Receive Engine
- Compliant with OCP 3.1 specification
- Supports access for Ring and Chained Descriptor Structures
- Configurable Transmit and Receive Engine based on Host Memory Data Width
- Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian)
- Supports configurable DMA Transmit and DMA Receive FIFO based on Host Memory Data width
- Supports hardware DMA Control registers that can be written and read by CPU
- Round Robin algorithm for arbitration between DMA Transmit and Receive Engine to access SOC Master Bus
- SOC Master bus can be AXI/AHB/APB/OCP/Tilelink/Wishbone
- Supports OCP Slave bus
- Uses SOC Slave Interface to get Receive and Transmit descriptors and transfer the data to/from the system memory from/to FIFO inside the DMA controller
- User logic to map data fetched from Host to IP core or from IP core to host
- Supports following DMA transfers
- Memory to Memory
- Memory to Peripheral
- Peripheral to Memory
- Peripheral to Peripheral
- Supports Sideband DMA request and Grant based triggering of transfers as on option for peripherals
- Supports Scatter Gathers list
- Supports 8/16/32/64/128/256 bit wide data transfers
- Supports QoS per channel if SOC master interface supports Qos.
- Supports programmable burst capability per SOC master
- Supports both single data and burst data transfers, with burst size based on the burst length field in the DMA control registers
- DMA supports full duplex operation, processing read and write transfers at the same time
- Supports Link list based processor for autonomous operation
- Interface widths can be controller for each SOC master interface
- Supports access for Ring and Chained Descriptor Structures
- Configurable Transmit and Receive Engine based on Host Memory Data Width
- Configurable support by DMA Transmit and Receive Engine for both of the endianness of the host memory (Little / Big Endian)
- Supports configurable DMA Transmit and DMA Receive FIFO based on Host Memory Data width
- Supports hardware DMA Control registers that can be written and read by CPU
- Supports different algorithms for selecting which channel to process and how long to process.
- Generate full 32-bit addresses on the SOC master interface
- Supports per Channel Interrupt output
- Supports up to 64 MB transfer per Buffer Descriptor (BD)
- Supports both single data and burst data transfers, with burst size based on the burst length field in the DMA control registers
- DMA supports full duplex operation, processing read and write transfers at the same time
- Interrupts CPU on completion of a DMA transfer or an error
- Fully synthesizable
- Static synchronous design
- Benefits
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- Single Site license option is provided to companies designing in a single site
- Multi Sites license option is provided to companies designing in multiple sites
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs
- Deliverables
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SmartDV's DMA Controller with OCP IP contains following
- The DMA Controller with OCP interface is available in Source and netlist products
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes
