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DISPLAY PORT RECEIVER IIP

DISPLAY PORT RECEIVER IIP

Display Port Receiver core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DISPLAY PORT RECEIVER IIP is proven in FPGA environment. The host interface of the Display Port can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

DISPLAY PORT RECEIVER IIP is supported natively in Verilog and VHDL

Features
  • Compliant with Display Port version 2.0 specification.
  • Supports full Display port Receiver functionality
  • Supports multi lanes upto 4 lanes
  • Supports 10bit, 20bit, 40bit, and 80bit parallel interfaces
  • Supports 1/4/8/16 pixels per clock
  • Supports control symbols for framing (Both Default & Enhanced framing mode)
  • Supports interlaced & non-interlaced video stream
  • Supports backwards compatibility
  • Supports nibble interleaving (ECC)
  • Supports main link, Aux link and Hot plug functionality
  • Supports fast link training
  • Supports full link training
  • Supports skip the link training
  • Supports I2C over AUX CH and EDID
  • Supports symbol Stuffing and Transfer Unit
  • Supports 3D stereo
  • Supports ANSI10B8B decoding.
  • Supports 132b/128b channel decoding.
  • Supports all the video formats which are mentioned in Display Port upto 2.0 version
  • Supports all secondary packet formats which are mentioned in Display Port upto 2.0 version.
  • Supports HPD based link training
  • Supports DPCD registers upto Display Port version 2.0 specification
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420 , Y-Only and RAW color format
  • Supports main stream attribute (MSA) packets
  • Supports following Secondary packets,
    • Audio timestamp
    • Audio stream
    • Extension
    • Audio copy management
    • ISRC
    • VSC
    • Camera SDP 8 to 15
    • Info frame formats
    • VSC extension VESA
    • VSC extension CEA
    • Picture Parameter Set(PPS)
    • Adaptive-Sync SDP
  • Supports Split SDP for both SST and MST mode
  • Supports all audio formats which are mentioned in IEC 60958-1,IEC 60958-3,IEC 60958-4,IEC 61937-1,IEC 61937-3,CEA/CTA 861-F,861-G
  • Supports training pattern sequence (TPS2,TPS3,TPS4)
  • Supports descrambler as in Display port specification
  • Descrambler can be enabled or disabled dynamically
  • Supports descrambler reset after every 512th symbol
  • Supports Multi Stream Transport (MST) operation
  • Supports Advanced Link Power Management to reduce wake latency
  • Supports GTC-based video timing synchronization
  • Supports Display Stream De-Compression (DSC) up to version 1.2a
  • Supports high-bandwidth Digital Content Protection System up to version2.3 (HDCP v2.3)
    • Supports for full authentication
    • Supports for bypass the authentication
  • Supports Horizontal Blanking Expansion
  • Supports RBR, HBR, HBR2, HBR3 and Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link rates
  • Supports Panel Replay
  • Detects and reports the following errors,
    • Invalid control character
    • Invalid data character
    • Invalid 10bit code
    • Sync errors
    • Scrambler errors
    • Single and multi-bit ECC errors
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

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    SmartDV's Display Port Receiver IP contains following

  • The Display Port Receiver interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

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