Display Port Transmitter core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DISPLAY PORT TRANSMITTER IIP is proven in FPGA environment. The host interface of the Display Port can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
DISPLAY PORT TRANSMITTER IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with Display Port version 2.0 specification.
- Supports full Display port Transmitter functionality
- Supports multi lanes upto 4 lanes
- Supports 10bit, 20bit, 40bit and 80bit parallel interfaces
- Supports 1/4/8/16 pixel per clock
- Supports control symbols for framing (Both Default & Enhanced framing mode)
- Supports interlaced & non-interlaced video stream
- Supports nibble interleaving (ECC)
- Supports main link, Aux link and Hot plug functionality
- Supports fast link training
- Supports full link training
- Supports skip the link training
- Supports I2C over AUX CH and EDID
- Supports symbol Stuffing and Transfer Unit
- Supports 3D stereo
- Supports ANSI8B10B encoding
- Supports 128b/132b channel encoding
- Supports all the video formats which are mentioned in Display Port upto 2.0 version
- Supports all secondary packet formats which are mentioned in Display Port upto 2.0 version.
- Supports HPD based link training
- Supports RGB, YCBCR444, YCBCR422, YCBCR420, Y-Only and RAW color format
- Supports main stream attribute (MSA) packets
- Supports following Secondary packets,
- Audio timestamp
- Audio stream
- Extension
- Audio copy management
- ISRC
- VSC
- Camera SDP 8 to 15
- Info frame formats
- VSC extension VESA
- VSC extension CEA
- Picture Parameter Set(PPS)
- Adaptive-Sync SDP
- Supports Split SDP for both SST and MST mode
- Supports all audio formats which are mentioned in IEC 60958-1,IEC 60958-3,IEC 60958-4,IEC 61937-1,IEC 61937-3,CEA/CTA 861-F,861-G
- Supports training pattern sequence (TPS2,TPS3,TPS4)
- Supports scrambler as in Display port specification
- Scrambler can be enabled or disabled dynamically
- Supports scrambler reset after every 512th symbol
- Supports Multi Stream Transport (MST) operation
- Supports Advanced Link Power Management to reduce wake latency
- Supports GTC-based video timing synchronization
- Supports Display Stream Compression (DSC) up to version 1.2a
- Supports high-bandwidth Digital Content Protection System upto version2.3 (HDCP v2.3)
- Supports for full authentication
- Supports for bypass the authentication
- Supports Horizontal Blanking Expansion
- Supports Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link rates
- Supports Panel Replay
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's Display Port Transmitter IP contains following
- The Display Port Transmitter interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
- ISO26262 Safety Manual (SAM) Document
- ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
