SPDIF interface provides full support for the two-wire SPDIF synchronous serial interface, compatible with IEC 60958 and IEC61937 specification. Through its SPDIF compatibility, it provides a simple interface to a wide range of low-cost devices. SPDIF IP is proven in FPGA environment.The host interface of the SPDIF can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
SPDIF IP is supported natively in Verilog and VHDL
- Features
-
- Full SPDIF functionality as per specs.
- Supports Variable sampling/Driving rates (32 kHz/44.1 kHz/48 kHz/88.2 kHz/96 kHz/176.4 kHz/192 kHz)
- Supports 20/24 bit samples
- Synchronization holds in the under-run condition, clock recovery from the SPDIF data stream.
- Sample rate detection from the received data stream
- Supports both transmit and receive function.
- Options Host control interface (DMA engine).
- Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
-
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- SPDIF IP
-
SmartDV's SPDIF IP contains following.
- The SPDIF interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog or VHDL or SystemC source code
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
- Documentation contains User's Guide and Release notes.
