SPI Master is full-featured,easy-to-use,synthesizable design,compatible with SPI Block Guide 4.01 Complient.Through its SPI Master compatibility, it provides a simple interface to a wide range of low-cost devices.SPI Master IIP is proven in FPGA environment. Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. The host interface of the SPI Master can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
SPI Master IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with SPI Block Guide 4.01 Standard
- Complaint to TI and National Modes (Microwire)
- Supports 3 wire and 4 wire operation
- Supports DDR mode of operation
- Single, dual, quad and octal serial data lines
- In built DMA (Host Controller Interface) controller
- Up to 16 slaves supported under master control
- Supports multi master operation
- Mode fault error flag with CPU interrupt capability
- Serial clock with programmable polarity and phase
- LSB or MSB mode
- Supports flexible Serial clock generation
- Full duplex and half duplex operation
- Bi-directional mode
- Supports any kind of SPI transactions to access any kind of SPI slave device
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's SPI Master IP contains following
- The SPI Master interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
