SWP Slave is full-featured,easy-to-use,synthesizable design,compatible with ETSI TS 102 613 and ETSI TS 102 221 Specification Complient.Through its SWP Slave compatibility, it provides a simple interface to a wide range of low-cost devices.SWP Slave IIP is proven in FPGA environment. Designed to work with a wide variety of SWP bus variants, the core supports run-time control of several SWP protocol parameters. The host interface of the SWP Slave can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
SWP Slave IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with ETSI TS 102 613 and ETSI TS 102 221 Specification.
- Complete SWP Uicc functionality.
- Supports SWP interface between CLF and UICC
- Supports different types of layers,
- Physical layer
- Data link layer
- MAC layer
- LLC layer
- Supports contacts activation and deactivation
- Supports ACT LLC, SHDLC LLC and CLT LLC
- Support SHDLC LLC frame types,
- I-Frames
- S-Frames
- U-Frames
- Supports configurable timing functions.
- Acknowledge time
- Guarding/transmit time
- Connection time
- Automatic handling of
- End of frame (EOF)
- stuffing bits
- CRC-16
- calculation and generation in transmission
- calculation and checking in reception
- 32-bit Transmit data register
- 32-bit Receive data register
- CRC error, underrun, overrun flags
- Frame reception and transmission complete flags
- Slave resume detection flag
- Exit from Stop 1 mode with a RESUME by slave event
- Loopback mode for test purpose
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's SWP Slave IP contains following
- The SWP Slave interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
