DDR3 DFI Verification IP provides an smart way to verify the DDR3 DFI component of a SOC or a ASIC. The SmartDV's DDR3 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.
DDR3 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR3 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with DFI version 2.0 or higher Specifications.
- DFI-DDR3 Applies to :
- DDR3 protocol standard JESD79-3F Specification
- Supports all the Interface Groups.
- Supports Write Transactions with DM
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports DFI Read/Write Chip Select.
- Supports Training interface
- Gate Training
- Read data eye training
- Write leveling
- Write DQ Training
- Supports Low power control features.
- Supports Error signaling.
- Supports Per-Slice Read Leveling.
- Supports Inactive CS.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI version 2.0 or higher Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster test bench development and more complete verification of DDR3 DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- DDR3 DFI Verification Env
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SmartDV's DDR3 DFI Verification env contains following.
- Complete regression suite containing all the DDR3 DFI testcases.
- Complete UVM/OVM sequence library for DDR3 DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
