OCTARAM Memory Model provides an smart way to verify the OCTARAM component of a SOC or a ASIC. The SmartDV's OCTARAM memory model is fully compliant with standard OCTARAM Specification and provides the following features. Better than Denali Memory Models.
OCTARAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
OCTARAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
-
- Supports OCTARAM memory devices from all leading vendors.
- Supports 100% of OCTARAM protocol standard specification.
- Supports all the OCTARAM commands as per the specification.
- Supports device density up to 256MB.
- Quickly validates the implementation of the OCTARAM protocol.
- Supports wrap and hybrid burst length 16, 32, 64 and 128.
- Supports clock rate up to 200MHz.
- Supports wrap and hybrid wrap burst transfer.
- Supports linear burst command for read and write operation.
- Supports programmable read/write latencies.
- Supports mode register programming.
- Supports write data mask operation.
- Supports deep sleep mode.
- Supports ultra-low power half sleep mode with data retained.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Supports callbacks for user to get command data on bus.
- Constantly monitors OCTARAM behavior during simulation.
- Bus-accurate timing for min, max and typical values.
- Models, detects and notifies the test bench of significant events such as
- transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
-
- Faster testbench development and more complete verification of OCTARAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- OCTARAM Verification Env
-
SmartDV's OCTARAM Verification env contains following.
- Complete regression suite containing all the OCTARAM testcases.
- Complete UVM/OVM sequence library for OCTARAM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
