DDR5 DFI Synthesizable Transactor provides a smart way to verify the DDR5 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR5 DFI Synthesizable Transactor is fully compliant with standard DFI 5.0 Specification and provides the following features.
- Features
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- Compliant with DFI 5.0 Specification.
- DFI-DDR5 Applies to :
- DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft) Specifications
- Supports all Interface Groups.
- Supports Write Transactions with Data mask/Write DBI.
- Supports Write Transactions with data CRC
- Supports Read Transactions with CRC.
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports Low power control features.
- Supports Error signaling.
- Supports DFI Read/Write Chip Select.
- Supports 3DS Stack.
- Supports Inactive CS.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 5.0 Specification
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- DDR5 DFI Synthesizable Transactor Env
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SmartDV's DDR5 DFI Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the DDR5 DFI testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
