MIPI A-PHY provides an efficient and simple way to verify the MIPI A-PHY. The SmartDV Verification IP for MIPI A-PHY is fully compliant with MIPI A-PHY 1.0 and 1.1 Specification and provides the following features.
MIPI A-PHY Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MIPI A-PHY Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Implemented in native OpenVera, SystemVerilog, Verilog and SystemC.
- Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
- Supports MIPI A-PHY specification 1.0 and 1.1.
- Supports single lane and dual lane, point-to-point and serial communication technology.
- Supports PHY layer and Data link layer features.
- MIPI A-PHY provides a main unidirectional data stream and a bi-directional low- throughput command and control data stream, and can optionally also deliver the required power supply to peripheral units (i.e., the sensors and/or displays at the edge of the network) directly via the A-PHY data line.
- The model has a rich set of configuration parameters to control MIPI A-PHY functionality.
- Support APPI interface between MIPI A-PHY and Native protocol.
- Support multiple speed gears ranging from 2Gbps up to 32 Gbps.
- Support 5 discrete Downlink Gears: G1, G2, G3, G4, and G5 and Uplink shall be 200Mbps at U1 and U2 gears
- Support two types of profiles :
- Profile 1 (P1-NRZ 8B/10B)
- Profile 2 (P2 -PAM 4, 8 ,16)
- Support clock recovery, Sink Transmitter shall use the recovered Source clock to generate the proper Sink transmit clock, to reach the proper port rate.
- Support Re transmission request / ACK types.
- Support Scrambler as per specs.
- Support Re-Training sequence.
- Support two types of Startup Procedure:
- Mission Mode startup
- Unidirectional startup
- Support Wake-Up protocol and below Mode of operation :
- Non active Mode
- Active Mode
- Implements below PHY layer architecture :
- MIPI A-PHY P1 G1/G2 Architecture
- RTS By-Pass
- 8B/10B PCS
- PMD
- MIPI A-PHY P2 G1/G2 Architecture
- RTS for Uplink and Downlink
- 8B/10B PCS
- PMD
- MIPI A-PHY G3-G5 Architecture
- RTS for Uplink and Downlink
- 8B/10B PCS for Uplink
- PAM 4, 8 ,16 PCS for Downlink
- PMD
- Support below Data Link feature:
- Link service
- Local function
- Multi-port function
- Network function
- Monitor, Detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Supports constraints Randomization.
- Status counters for various events in bus.
- Callbacks in transmitter and receiver for various events.
- MIPI A-PHY Verification IP comes with complete test suite to test every feature of MIPI A-PHY specification.
- Functional coverage for complete MIPI A-PHY features.
- Benefits
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- Faster testbench development and more complete verification of MIPI A-PHY designs.
- Easy to use command interface simplifies testbench control and configuration of Tx,Rx and monitor
- Simplifies results analysis.
- Integrates easily into OpenVera, SystemVerilog, Verilog, SystemC, Specman E.
- Runs in every major simulation environment.
- MIPI APHY Verification Env
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SmartDV's MIPI A-PHY Verification env contains following.
- Complete regression suite containing all the MIPI APHY testcases.
- Examples showing how to connect various components, and usage of Tx,Rx and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
- Smart VIPDebug
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Smart VIPDebug provides easy way to debug the MIPI APHY Verification IP Protocol. This links waveform, log file with specs and makes debugging easier
Smart VIPDebug supports both VCD and FSDB files for debugging.
