SPI/MACRONIX Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/MACRONIX Verification IP is fully compliant with SPI Block Guide V04.01 of the Macronixs MX25L51245G,MX25L25645G,MX25L12872F Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
SPI/MACRONIX Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SPI/MACRONIX Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Follows Macronix specification as defined in Macronix MX25L51245G,MX25L25645G,MX25L12872F devices
- Supports Serial Peripheral Interfaces Mode 0 and Mode 3
- Supports Single I/O, Dual I/O and Quad I/O
- Supports clock frequency up to 166MHz for all protocols
- Supports Fast Read, 2READ, DREAD, 4READ,QREAD instructions
- Supports DTR (Double Transfer Rate) Mode
- Supports Configurable dummy cycle number for fast read operation
- Supports Quad Peripheral Interface (QPI) available
- Supports Block Erase command
- Supports Quad Input/Output page program(4PP) to enhance
- Supports Advanced Security Features and Block lock protection
- Supports Additional 4K bit security OTP
- Supports Advanced sector protections
- Supports Program/Erase Suspend and Resume operation
- Support Serial Flash Discoverable Parameters (SFDP) mode
- Support Master and Slave Mode
- Supports customized single/dual/quad modes for Command, Address and Data phase
- Supports configurable dummy cycles
- Supports configurable memory density
- Supports backdoor access for memory and registers
- Built in functional coverage analysis.
- Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI/MACRONIX bus.
- SPI/MACRONIX Slave can be configured as standard device or can use FIFO for data passing.
- Master contains rich set of commands for both standard device and FIFO model mode.
- Benefits
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- Faster testbench development and more complete verification of Macronix designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- SPI Verification Env
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SmartDV's SPI/MACRONIX Verification env contains following.
- Complete regression suite containing all the SPI/MACRONIX testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
