SPI/RTC (Real time counter) Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/RTC Verification IP is fully compliant with SPI Block Guide V04.01 of the Motorola's M68HC11 user manual rev 5.0 SPI-Bus Specification and DS3234 maxim_spi_rtc and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
SPI/RTC Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SPI/RTC Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Follows RTC basic specification as defined in DS3234 maxim_spi_rtc.
- Support Master and Slave Mode.
- Supports data width of 8 bit.
- Support baud rate selection.
- Support internal clock division check.
- Support single and burst transfer mode.
- Support on the fly generation of data.
- Supports constraints Randomization.
- Glitch insertion and detection.
- Built in functional coverage analysis.
- Status counters for various events on bus.
- Supports single,dual bus width operation.
- Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI/RTC.
- SPI/RTC Slave can be configured as standard device or can use FIFO for data passing.
- Master contains rich set of commands for both standard device and FIFO model mode.
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
- SPI/RTC Verification IP comes with complete test suite to test every feature of SPI/RTC specification.
- Benefits
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- Faster testbench development and more complete verification of SPI/RTC designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- SPI/RTC Verification Env
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SmartDV's SPI/RTC Verification env contains following.
- Complete regression suite containing all the SPI/RTC testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
